--rundy 1
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity invrunda1 is
    Port ( ri : in  STD_LOGIC_VECTOR (127 downto 0);
		rk: in STD_LOGIC_VECTOR (127 downto 0);
		ro : out  STD_LOGIC_VECTOR (127 downto 0));
end invrunda1;

architecture Behavioral of invrunda1 is
component keymix is 
    Port ( kid : in  STD_LOGIC_VECTOR (127 downto 0);
		kik : in STD_LOGIC_VECTOR (127 downto 0);
		ko : out  STD_LOGIC_VECTOR (127 downto 0));
end component keymix;

component InSbox0set is
    Port ( si : in  STD_LOGIC_VECTOR (127 downto 0);
		so : out  STD_LOGIC_VECTOR (127 downto 0));
end component InSbox0set;

component invlineartransf is
    Port ( li : in  STD_LOGIC_VECTOR (127 downto 0);
		lo : out  STD_LOGIC_VECTOR (127 downto 0));
end component invlineartransf;

signal n1, n2 : STD_LOGIC_VECTOR (127 downto 0);
begin
b3: invlineartransf port map(ri,n2);
b2: InSbox0set port map(n2,n1);
b1: keymix port map(n1,rk,ro);
end Behavioral;